This disclosure relates generally to timed input and output operations and circuits in electronics circuits. This disclosure more specifically relates to memory read and write method and apparatus with improved performance and reliability.
Certain timed input and output operations, such as READ and WRITE operations for memory devices, such as memory arrays, entail input and/or output events synchronized with clock pulses. In reading and writing to a memory array, for example, a train of clock pulses may be applied to the drivers for respective rows of memory cells to enable the read or write operations of selected rows at each clock pulse. Fast and reliable READ and WRITE operations may be achieved by shorter clock cycles and reduced time lapse between the clock pulses and respective READ or WRITE operations.